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 STG4159
Low voltage 0.3 max single SPDT switch with break-before-make feature and 10kV contact ESD protection
Features

Wide operating voltage range: VCC (OPR) = 1.65V to 4.8V Low power dissipation: ICC = 0.2A (max.) at TA = 85C Low "ON" resistance VIN = 0V: - RON = 0.40 (max. TA = 25C) at VCC = 2.25V - RON = 0.35 (max. TA = 25C) at VCC = 3.0V - RON = 0.30 (max. TA = 25C) at VCC = 4.3V
Flip-Chip7
Description
The STG4159 is a high-speed CMOS low voltage single analog SPDT (Single Pole Dual Throw) switch or 2:1 multiplexer/demultiplexer switch fabricated in silicon gate C2MOS technology. It is designed to operate from 1.65V to 4.58V, making this device ideal for portable applications. It offers low ON-resistance (0.45) at VCC = 4.3V. The SEL inputs are provided to control the switches. The switch S1 is ON (connected to common Port D) when the SEL input is held high and OFF (high impedance state exists between the two ports) when SEL is held low; the switch S2 is ON (it is connected to common Port D) when the SEL input is held low and OFF (high impedance state exist between the two ports) when SEL is held high. Additional key features are fast switching speed, break-before-make delay time and ultra low power consumption. All inputs and outputs are equipped with protection circuits against static discharge, giving them ESD immunity and transient excess voltage.

Separate supply voltage for switch and control pin Latch-up performance exceeds 100mA per JESD 78, Class II ESD performance tested on common channel (D pin) - 10kV IEC-61000-4-2 ESD, contact discharge - 15kV IEC-61000-4-2 ESD, air discharge ESD performance test on all other pins - 10kV IEC-61000-4-2 ESD, contact discharge - 500V machine model (JESD22 A115-A) - 1500V charged-device model (JESD22 C101)
Table 1.
Device summary
Part number STG4159 STG4159BJR Package Flip-Chip7 Flip-Chip7 Rev 3 Packaging Tube Tape and reel 1/18
www.st.com 18
April 2007
Contents
STG4159
Contents
1 2 3 4 5 6 Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Test circuits ................................................. 9
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
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STG4159
Logic diagram
1
Logic diagram
Figure 1. Functional diagram
D
S1 S2
SEL
Figure 2. Input equivalent circuit
Table 2.
Truth table
SEL H L Switch S1 ON OFF (1) Switch S2 OFF (1) ON
1. High Impedance
3/18
Logic diagram Figure 3. Pin connection (bump side view)
STG4159
Table 3.
Pin description
Symbol S1, S2 D SEL VCC VL GND Name and function Independent channels Common channel Control Positive supply voltage Logic supply voltage Ground (0V)
Flip-Chip 1, 3 7 6 5 4 8
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STG4159
Maximum rating
2
Maximum rating
Stressing the device above the rating listed in the "Absolute maximum ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 4.
Symbol VCC VL VI VIC VO IIKC IIK IOK IO IOP Supply voltage Logic supply voltage DC input voltage DC control input voltage DC output voltage DC input diode current on control pin (VSEL < 0V) DC input diode current (VSEL < 0V) DC output diode current DC output current DC output current peak (pulse at 1ms, 10% duty cycle)
Absolute maximum ratings
Parameter Value -0.5 to 5.5 -0.5 to 5.5 -0.5 to VCC + 0.5 -0.5 to VL + 0.5 -0.5 to VCC + 0.5 -50 50 20 300 500 100 500 -50 to 105 260 Unit V V V V V mA mA mA mA mA mA mW C C
ICC or IGND DC VCC or ground current PD Tstg TL
1.
Power dissipation at TA = 70C (1) Storage temperature Lead temperature (10 sec)
Derate above 70C by 18.5mW/C
Table 5.
Symbol VCC VL VI VIC VO Top dt/dv
Recommended operating conditions
Parameter Supply voltage (1) Logic supply voltage (2) Input voltage Control input voltage Output voltage Operating temperature Input rise and fall time control input VL = 1.65V to 2.7V VL = 3.0V to 4.8V Value 1.65 to 4.8 1.65 to VCC 0 to VCC 0 to VL 0 to VCC -40 to 85 0 to 20 ns/V 0 to 10 Unit V V V V V C
1. Truth Table guaranteed: 1.65V to 4.8V 2. VL pin should not be left floating.
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Electrical characteristics
STG4159
3
Electrical characteristics
Table 6. DC specifications
Test conditions Symbol Parameter VCC (V) VL (V) 1.65-1.95 VIH High level input voltage 1.65-4.3 2.3-2.7 3.0-3.6 4.3 1.65-1.95 VIL Low level input voltage 1.65-4.3 2.3-2.7 3.0-3.6 4.3 1.8 2.25 RON ON resistance 3 3.7 4.3 1.8 RON ON resistance match between channels (1) 2.25 3 3.7 4.3 1.8 2.5 RFLAT ON resistance flatness (2) 3 3.7 4.3 IOFF ION ID Sn OFF state leakage current Sn ON state leakage current D ON state leakage current 1.65-4.3 1.65 - 4.3 VS=0 to VCC VD=0 to VCC VS=0 to VCC VD=Open VS=Open VD=0 to VCC -20 1.65 - 4.3 VS=0V to VCC IS=100mA 1.65-4.3 VS=0V to VCC IS=100mA 1.65-4.3 VS=0V to VCC IS=100mA 0.49 0.30 0.25 0.22 0.21 5 3 3 3 3 300 130 90 90 90 400 170 120 120 120 20 -300 450 230 170 170 170 300 nA m m Value TA = 25C -40 to 85C Unit
Min. Typ. Max. Min. Max. 1.25 1.75 2.35 2.8 0.6 0.8 1.05 1.5 0.65 0.40 0.35 0.32 0.30 1.25 1.75 2.35 2.8 0.6 0.8 1.05 1.5 0.85 0.50 0.45 0.42 0.40 V V
1.65-4.3 1.65 - 4.3
-20
20
-100
100
nA
1.65-4.3 1.65 - 4.3
-20
20
-100
100
nA
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STG4159
Table 6. DC specifications
Test conditions Symbol Parameter VCC (V) Quiescent supply current SEL leakage current VL (V) VSEL=VCC or GND VSEL=4.3V or GND
Electrical characteristics
Value TA = 25C -40 to 85C Unit
Min. Typ. Max. Min. Max. ICC ISEL 1.65-4.3 1.65 - 4.3 1.65-4.3 1.65 - 4.3 -0.05 -0.1 0.05 0.1 -0.2 -1 0.2 1 A A
1. RON = RON(Max) - RON(Min) 2. Flatness is defined as the difference between the maximum and minimum value of on-resistance as measured over the specified analog signal ranges.
Table 7.
AC electrical characteristics (CL = 35pF, RL = 50, tr = tf 5ns)
Test conditions Value TA = 25C VCC (V) 1.65-1.95 VL (V) Min. Typ. 0.13 0.15 1.65-4.3 3.0-3.3 3.6-4.3 1.65-1.95 VS = VCC 1.65-4.3 RL = 50 CL = 30pF 0.16 0.16 95 48 33 29 12 VS = VCC 1.65-4.3 RL = 50 CL = 30pF 10 CL = 35pF 1.65-4.3 RL = 50 VS = VCC/2 10 5 5 12 13 13 42 22 ns 15 12 83 1.65-4.3 3.0-3.3 3.6-4.3 CL = 1nF VGEN = 0V 98 pC 114 140 123 62 43 38 15 16 17 17 160 80 ns 56 49 20 21 ns 22 22 ns Max. Min. Max. -40 to 85C Unit
Symbol
Parameter
tPLH, tPHL
Propagation delay
2.3-2.7
tON
TURN-ON time
2.3-2.7 3-3.6 4.3 1.65-1.95
tOFF
TURN-OFF time
2.3-2.7 3-3.6 4.3 1.65-1.95
tD
Breakbefore-make time delay
2.3-2.7 3-3.6 4.3 1.65-1.95
Q
Charge injection
2.3-2.7
7/18
Electrical characteristics Table 8. Analog switch characteristics (CL = 5pF, RL = 50, TA = 25C)
Test conditions Symbol Parameter VCC (V) Off Isolation
(1)
STG4159
Value TA = 25C -40 to 85C Unit Min. Max. dB
VL (V) Min. Typ. -69 Max. VS = 1VRMS f = 100kHz VS = 1VRMS f = 100kHz RL = 600
OIRR
1.65-4.3
4.3
Xtalk
Crosstalk
1.65-4.3
4.3
-69
dB
THD
Total harmonic distortion
CL = 50pF 2.3-4.3 4.3 VS = VCC VPP f = 600Hz to 20kHz 1.65-4.3 4.3 RL = 50 28 MHz 0.01 %
BW
-3dB Bandwidth (switch ON) Control pin input capacitance Sn port capacitance D port capacitance when switch is enabled
CSEL
1.8-4.3
1.8-4.3
VL = VCC
30
CSn
1.8-4.3
1.8-4.3
VL = VCC
94
pF
CD
1.8-4.3
1.8-4.3
VL = VCC
227
1.
OFF-isolation = 20 log10 (VD/VS), VD = output, VS = input to off switch
8/18
STG4159
Test circuits
4
Figure 4.
Test circuits
ON-Resistance Figure 5. Bandwidth
Figure 6.
OFF Leakage
Figure 7.
Channel to channel crosstalk
Figure 8.
OFF Isolation
9/18
Test circuits
STG4159
Figure 9.
Test circuit
Note: 1 CL = 5/35pF or equivalent: (includes jig capacitance) 2 RL = 50 or equivalent 3 RT = ZOUT of pulse generator (typically 50) Figure 10. Break-before-make time delay
10/18
STG4159
Figure 11. Switching time and charge injection (VGEN = 0V, RGEN = 0, RL = 1M, CL = 100pF)
Test circuits
Figure 12. Turn ON, turn OFF delay time
11/18
Package mechanical data
STG4159
5
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
12/18
STG4159
Table 9.
Dim. Min A A1 A2 b D D1 E E1 e f ccc 0.45 2.018 0.265 1.018 0.585 0.21 Typ 0.65 0.25 0.4 0.315 1.068 0.5 2.068 1.5 0.5 0.284 0.08 0.55 2.118 0.365 1.118 Max 0.715 0.29 Min 0.60 0.22 0.38 0.290 1.053 0.49 2.053 1.49 0.46 0.272
Package mechanical data Flip-Chip7 mechanical data
Data book (mm) Drawing (mm) Typ 0.65 0.25 0.4 0.315 1.068 0.5 2.068 1.5 0.5 0.284 0.08 Max 0.70 0.28 0.42 0.340 1.083 0.51 2.083 1.51 0.54 0.292
Note: 1 The terminal Pin 1 on the bumps side is identified by a distinguishing feature (for instance by a circular "clear area" - typically 0.1mm diameter - ) The terminal Pin 1 on the backside of the product is identified by a distinguishing feature (for instance by a circular "dot" - typically 0.5mm diameter - ).
Figure 13. Package dimensions
13/18
Package mechanical data Figure 14. Foot print recommendations
STG4159
Figure 15. Marking Dot, ST Logo S1 = Marking V = Manufacturing Location yww = Datecode (y = year, ww = week)
Figure 16. Flip-Chip7 tape specification
14/18
STG4159
Figure 17. Flip-Chip7 reel information
Package mechanical data
15/18
Package mechanical data Figure 18. Flip-Chip7 reel information
STG4159
16/18
STG4159
Revision history
6
Revision history
Table 10.
Date 05-May-2006 22-Nov-2006 17-Apr-2007
Revision history
Revision 1 2 3 First release Schematic Figure 1 on page 3 updated Typo in cover page description Changes
17/18
STG4159
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